1. Field of Invention
The present invention relates generally to the field of electronic data storage devices. More particularly, the present invention relates to non-volatile multi-level-cell semiconductor memory devices and a method for reducing program-verify time in non-volatile multi-level-cell semiconductor memory devices.
2. Description of Related Art
Many electronic devices, such as computers, personal digital assistants, cellular telephones, digital cameras and similar systems and devices include processors and memory fabricated from semiconductors. The memory is used to store computer programs to be executed by the device and/or data operated on by the processors to achieve the functionality of the device. Many devices and systems require that this information be retained in permanent storagexe2x80x94non-volatile mediumxe2x80x94so that the data and computer programs remain when power is removed.
Conventional semiconductor memory devices store bits of information in memory cells. The typical memory cell comprises an access transistor and a storage element such as a capacitor. Data is represented in binary notation with a xe2x80x9c1xe2x80x9d or a xe2x80x9c0,xe2x80x9d depending on the charge stored at the location. Such devices, however, require constant ambient power in order to retain the charge. Therefore, the data stored in such memory devices are susceptible to power loss.
Semiconductor memory devices that do not require ambient power to retain the data stored therein have been developed. These devices have been termed xe2x80x9cnon-volatilexe2x80x9d semiconductor memory devices. In common designs for non-volatile semiconductor memory devices, data is internally organized in an array of sectors, each comprising a plurality of memory cells. Each sector is partitioned into segments termed a page, each page partitioned into segments termed a word, and each word partitioned into memory cells. Data is accessed for reading and programming by page, while the entire sector is accessed for erasing.
A few examples of non-volatile semiconductor memory devices include Read Only Memory (ROM), Programmable Read Only Memory (PROM), and Erasable Programmable Read Only Memory (EPROM). While conventional EPROM""s provide reliable non-volatile storage, they typically may not be able to be reprogrammed in a practical matter. For example, EPROM""s typically require exposure to Ultraviolet light to erase. This often requires that the device be removed from its host to be erased. In many applications, removing the memory is not practical to reprogram.
An Electrically Erasable Programmable Read Only Memory (EEPROM) is a type of EPROM. An EEPROM is similar to an EPROM, but can be electrically reprogrammed with voltage pulses and without special hardware. An EEPROM has the disadvantages of being expensive and having a relatively limited life span, according to the number of erased and write operations.
Another type memory having similar properties to of non-volatile memory devices is the Static Random Access Memory (SRAM). The SRAM offers high operating speeds but only maintains its ability to retain the information stored therein while power is supplied to it. Therefore, to retain its non-volatility properties, it requires constant power from a battery or other similar energy storage device. This necessitates additional hardware to maintain power to the SRAM, which increases manufacturing cost and complexity. Further, the additional hardware may put undesirable constraints on the physical size of the design.
Flash memory (or Flash RAM) is another form of non-volatile memory devices. Flash Memory devices involve more complex processing and testing procedures than ROM, but have the advantage of electrical programming and erasing. In addition, Flash Memory has the additional ability of electrically selectively erasing all memory cells. One characteristic of flash memory is that individual memory cells must be erased before they can be reprogrammed. Using Flash Memory devices in circuitry permits in-circuit erasing and reprogramming of the device without having to remove the memory device. The bits in a flash memory device can be modified millions of times during the lifetime of the device. Conventional flash memory devices store a single bit of data per memory cell. Each memory cell is characterized by a threshold voltage (Vt). Within conventional flash memory devices, two possible threshold voltages (Vt) exist.
FIGS. 1 and 1a show an example of a typical configuration for a conventional flash memory cell 100 in a flash memory device. A Conventional flash memory cell 100 uses a memory cell transistor 101 having a substrate 104, a source 105, a drain 106, a gate 107, and a floating gate 102 structure. A thin insulating film 103 may also be located between the floating gate 102 and the substrate 104. Data in the flash memory device are programmed or erased by accumulation or evacuation of charge a floating gate 102. Programming of the memory cell 100 occurs by applying a sufficient voltage difference to the transistor to cause excess electrons to accumulate on the floating gate 102. The accumulation of the additional electrons on the floating gate 102 raises the charge on the gate and the transistor""s Vt. The transistor""s Vt is raised sufficiently above that of the applied voltage during read cycles Vr so that the transistor does not conduct during the read cycles. Therefore, a programmed memory cell 100 will not carry current, representing the logical value xe2x80x9c0.xe2x80x9d
The erasure of data in a memory cell 100 is caused by a process by which a sufficient voltage difference is applied to the memory cell transistor 101 to cause the excess electrons on the floating gate 102 in the memory cell transistor 101 to evacuate the floating gate 102. Thereby the transistor""s Vt is lowered below that of the voltage potential applied to the transistor to read data Vr. In the erased state, current can flow through the transistor. When Vr is applied, the current will flow through the transistor of the memory cell 100, representing a logical value xe2x80x9c1xe2x80x9d stored in the memory cell 100. The granularity by which a flash memory device can be programmed or erased may vary. Granularities down to the bit level programming/erasure are contemplated.
An example of a typical configuration for an integrated circuit including a flash memory array 200 and circuitry enabling programming, erasing, and reading for memory cells in the array 200 is shown in FIG. 2. The flash memory array 200 includes individual cells 202. Each cell 202 has a drain connected to a bitline 204; each bitline 204 is connected to a bitline pull up circuit 206 and column decoder 208. The sources of the array cells are connected to Vss, while their gates are each connected by a word-line 209 to a row decoder 210.
The row decoder 210 receives voltage signals from a power supply 212 and distributes the particular voltage signals to the word-lines as controlled by a row address received from a processor or state machine 214. Likewise, the bitline pull up circuit 206 receives voltage signals from the power supply 212 and distributes the particular voltage signals to the bitlines as controlled by a signal from the processor 214. Voltages provided by the power supply 212 are provided as controlled by signals received from processor 214.
The column decoder 208 provides signals from particular bitlines 204 to sense amplifiers or comparators 216 as controlled by a column address signal received from processor 214. The sense amplifiers 216 further receive voltage reference signals from reference circuit 218. The outputs from sense amplifiers 216 are then provided through data latches or buffers 220 to processor 214.
Programming of the flash memory array 200 is executed on a word-line basis. The word-line 209 is considered the row address. The word-line will cross multiple bit-lines 204. The bit-line 204 is considered the column address. Each bit-line 204 contains buffer logic to interface to the selected cell during program, read, and erase operations.
Flash memory devices, termed multi-level-cell (MLC) flash memory devices, have been developed. MLC flash memory designs provide for the storage of more than one bit of information within a memory cell. Whereas, a conventional memory cell depicts two data storage levels (logic states xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d), multi-level storage refers to the ability of a single memory cell to represent multiple bits of data. MLC flash memory designs make use of the analog range of threshold voltage for a conventional flash. As discussed above, the memory cell transistor can be programmed to a specified Vt at any level within a range of voltages for the transistor. In MLC flash memory designs, the range in which the Vt may be programmed is segmented into various levels and each segment is assigned a specific bit pattern. Specifically, multiple bits can be stored in a single transistor because the MLC memory cell can be programmed to within any one of the segmented levels, with each voltage level representing multiple bits of data. The memory cell is programmed to a specified data storage level within the range segmented for the discrete combination of bits of data to be stored by the MLC memory cell.
Tables 1, 2, and 3 show examples of data storage in conventional 1-bit memory designs, 2-bit MLC flash memory designs, and 3-bit flash memory designs. As shown in these tables, storage of xe2x80x9cNxe2x80x9d bits of data in MLC flash memory devices requires the threshold voltage level to be divided into 2N data storage levels. (e.g. 2 bits requires 4 levels of storage.). Present MLC designs provide for the storage of as many as 256 levels. It will be appreciated, however, that MLC designs having more levels are contemplated. The number of levels that can be programmed is limited, for example, by the accuracy of the voltage detection and comparison to a threshold and the precision with which the electrons can be placed on the floating gate.
Allowing multiple bits of data to be programmed into a single cell in the flash memory in such designs affords storage for larger amounts of data within the same density of conventional flash memory devices which ultimately results to a significant reduction in the cost to store data. The different data storage levels can be sustained over time in a flash memory, even after repeated accesses to read data from the cell. By way of example only, as shown in Table 3, eight data storage levels provide storage for three bits of data that would ordinarily require at least three memory cells in a conventional flash memory device. Accordingly, MLC designs that stores three bits of data per cell provides three times as much data storage as a conventional memory array of the same size.
Programming data into a MLC flash memory array typically involves a complex process. The memory array is erased before it is primed for programming. In general, to program data into a flash memory array, program and verify cycles are necessary. Prior techniques required the programming and verifying cycles in series for each data storage level. During the program cycle, a program voltage, sufficient to program the memory cell at the appropriate Vt level, is applied each selected memory cell to be programmed at that level. Referring again to FIG. 2, to program a MLC flash memory cell in the flash memory array 200, high gate-to-drain voltage are provided to the cell from power supply 212 while a source of the cell is grounded. By way of example, during programming typical gate voltage pulses of 18V are each applied to a cell, while a drain voltage of the cell is set to 3.3V and its source is grounded.
During the verify cycle, it is determined whether each selected memory cell is programmed at that level. When it is determined that the selected memory is not programmed according to the verify cycle, the program cycle on the selected memory cells is repeated. The program and verify cycles are repeated until it is determined that each selected memory cell is programmed according to the verify cycle.
When it is determined that each memory cell in the selected memory sector is programmed, memory cells for any remaining Vt levels are selected and the program and verify cycles are performed on those memory cells. The program verify cycles are repeated until all of the data has been verified as loaded. Accordingly, MLC flash memory designs that utilize 2N Vt levels to represent N bits require Nxe2x88x921 program verify levels to program the N logical bits, where N is a number selected from the set of positive integers.
Because the program rate varies from memory cell to memory cell, the time necessary to program each cell also varies. The program cycle extends for a sufficient time expected to program the selected memory cells and the verify cycle determines whether the program cycle was sufficient to program all selected memory cells. The program cycle is comparatively slower than the verify cycle. During the program cycle, the program voltage pulses are applied for sufficient time expected to allow the accumulation of electrons on the floating gate necessary to raise the Vt level to the desired range. Programming each memory cell can take several program pulses.
After each program pulse, a verify cycle occurs. Verification is needed because of variation in program speeds among the bit-cell population. Fast bits may achieve the desired Vt level in 5 program pulses. Slow bit-cells may require 10 program pulses to complete. The verification cycle guarantees that each cell is at a desired Vt state. The verification cycle allows specific bits to be disabled from further programming when the desired Vt level is achieved.
A memory cell that has been verified as programmed is unselected such that it is not subjected to further program cycles after it has been verified as programmed. FIG. 3 illustrates a selected and unselected bit-line during programming. The unselected memory cell (bit not to be programmed) is considered program inhibited because the bit-line is will not be subject to the effects of the program pulse. The selected memory cell (bit to be programmed) is referred to as program enabled and will be programmed during the program pulse.
As shown in FIG. 3, the program voltage Vpp (approximately 18V) will be applied to the selected word-line (column address). A substantially lesser voltage, such as 10V, will be applied to unselected word-lines. A selected word-line will have a strong electric field generated across the memory device. In particular, FIG. 3 shows that with Vss (approximately 0V) being applied to one end of a bit-line to be uninhibited, the source/drain regions of the bit-line will couple to 0V or ground. This will make the applied electric field appear much stronger so that effective programming can occur. A high electric field generated across the memory device will cause electron injection towards the floating gate of the selected cell exponentially proportional to strength of the field. This programming procedure results in an increase of a Vt for the memory cell to the desired level.
A program inhibited (unselected) word-line will not have a strong field across the transistor. FIG. 3 shows that with Vcc (approximately 3.0V) being applied at one end of a bit-line to be inhibited, the source/drain regions of bit-line will couple to 8V. This will make the applied field appear much weaker and no effective programming will occur.
Each memory cell requires application of a specific electric field to obtain the desired programmed Vt level. The magnitude of the electric field determines the program speed of the memory cell. Fast cells need less applied electric field while slow cells need more applied electric field. The electric field is applied through several program voltage pulses. The use of program voltage pulses allows for control program distributions. After each pulse, the cells are verified to determine whether the desired Vt has been achieved. Multiple program pulses allows for program inhibiting of fast bits and prevents possible data corruption from over-programmed cells. Verifying the memory cells provides for application of the program voltage pulses to selected memory cells to raise the Vt to a desired level while inhibiting application of the program voltage pulses to memory cells that are already programmed to the desired Vt level.
FIG. 4a illustrates a typical distribution map of individual Vt levels for a 2-bit MLC flash memory array, each cell capable of being programmed to one of four states. FIG. 4a shows the distribution of Vt within each level. All memory cells start in the erased state (Level E). Depending on data, specific bits will be programmed to the higher 3 levels. Programming the memory cell to the selected level changes the state of the memory cell from the erased xe2x80x9c11xe2x80x9d level to any of the three other levels xe2x80x9c10xe2x80x9d (Level 0), xe2x80x9c01xe2x80x9d (Level 1), or xe2x80x9c00xe2x80x9d (Level 2). As shown, the memory cells programmed to store Level 1 data-bits xe2x80x9c01xe2x80x9d in this example have a Vt value between Vt1 and Vt2. FIG. 4a illustrates a program margin between each program distribution. The program margin is selected based on the precision that the desired Vt for each level can be programmed and subsequently the data stored therein read. Once programmed, the data stored can be externally read-two bits in this example.
FIG. 4b illustrates the difference between the read and verify levels (Read Margin). In FIG. 4B, the read levels for level 0 and 1 are designated xe2x80x9cVt0xe2x80x9d and xe2x80x9cVt1xe2x80x9d, respectively, while the verify levels are Vvfy0, and Vvfy1, respectively. A verify operation is functionally the same as a read operation. The difference between the read and verify level is selected to supply a margin to compensate for reliability and functional variations (i.e. Vcc, temperature). In conventional MLC flash memory designs, verify cycles occur after each program cycle to determine if the memory has a desired Vt level.
Conventional programming and verifying flows independently program each Vt level. This is illustrated in FIG. 5 where programming pulses Pg0, Pg1, and Pg2 for programming levels 0, 1, and 2, respectively, are generated. By way of example, Pg2, Pg1, and Pg0 have values of 18V, 19V and 20V, respectively. The programming pulses each have a corresponding program verify pulse PV2, PV1 and PV0, respectively. By way of example, the verify pulse PV2 has a constant voltage of approximately 0.4V and a width of approximately 4 xcexcs, program verify pulse PV1 has a constant voltage of approximately 1.2V and a width of approximately 4 xcexcs and program verify pulse PV0 has a constant voltage of approximately 2.1V and a pulse width of approximately 4 xcexcs. If 10 pulses are required to program each level, then programming would constitute initially applying ten of the Pg2 V and PV2 V pulse pairs to program level 2. Next, ten of the Pg1 V and PV1 V pulse pairs are applied to program level 1. Finally, ten of the Pg0 V and PV0 pulse pairs are applied to program level 0. Thus, the total program time would take the time elapsed for 30 program pulses and 30 program-verify pulses.
A multi-level-cell 202 utilizes 2N Vt levels to represent N logical bits. Standard program times of MLC designs are 2Nxe2x88x921 times that of a single bit program time (SBPT). Again, a known programming distribution of Vt for two logical bits (N=2) in a single multi-level-cell 202 is shown in FIG. 4. In particular, four programming charge distributions E, 2, 1 and 0 are formed. All cells start in the erased statexe2x80x94Level E in this example. Therefore, only Levels 2, 1, and 0 need to be programmed. The centers of the programming charge distributions are preferably centered between the centers of the charge distributions for the reading pulses. The centers of the charge read distributions are labeled Vt0 Vt1 and Vt2 corresponding to Read Level 2, Read Level 1 and Read Level 0, respectively. Read level Vt0 typically has a value of approximately 0V, Read Level Vt1 a value of approximately 800 mV and Read Level Vt2 a value of approximately 1.6V. It is desired that there be no intersection between the programming and read distributions so that the read process can accurately predict the levels of the memory cell are properly programmed.
Table 2 below shows a preferred correspondence between the data storage levels E and 0-2, and the accessed logical bit values Q1, Q0, where Q1 and Q0 each represent a logical bit.
Since Level E is considered the default (erased) setting, there 2Nxe2x88x921 levelsxe2x80x94in the case N=2, there are 22xe2x88x921=3 levels (i.e. Level 2, 1, and 0)xe2x80x94that must be programmed, depending on loaded data. In a known manner of programming, each of the 22xe2x88x921 levels is programmed so that the programmed independently of the other levels. Each level is independently programmed so that the programmed inhibited bit-lines can be set. This separate programming results in the total programming time being equal to (2Nxe2x88x921)*SBPT. As the number of logical bits stored in the flash memory cell increases, the programming time becomes exponentially larger and more burdensome. For example, a 4-bit (N=4) MLC design can have a programming time that is 5 times greater than that of a 2-bit MLC design.
In order to achieve the above programming one or more pulses are applied to each Vt level separately. In the case of N=2, initially pulses of a voltage, such as 20V in the above example, are applied to the memory cells to be programmed to level 0. After level 2 is programmed, one or more pulses of a voltage, such as 19V in the above example, are applied to the next level 1 until all memory cells to be programmed to level 1 are programmed. Next, one or more pulses of a lower voltage, such as 18V in the above example, are applied to the next level 0 memory cells until level 0 is programmed. Note that the voltages of the pulses are dependent on the desired speed of programming.
To erase a cell in the flash memory array 200, relatively high substrate-to-gate voltage pulses are applied. The substrate 104 is charged to 19V while the gate 107 is grounded. The high potential will evacuate the electrons from the floating gate 102 and thus lower the Vt of the memory cell. The memory cell 202 with a lowered Vt will represent a logical xe2x80x9c1xe2x80x9d when the memory cell 202 is accessed for reading.
To read the state of a memory cell 202, a typical read level voltage is applied to the memory cell 202. The current output from the cell being read is received at an input of a number of the sense amplifiers 216 connected to the same bitline 204 as the memory cell 204 being read. A second input to each sense amplifier 216 is provided from a current reference 218. The current reference 218 provides a reference current to each sense amplifier, with a current level set equal to the current expected from a cell being read when programmed to a desired threshold voltage state. Binary outputs of the sense amplifiers 216 indicate if the cell being read is in a state that is greater than or less than the state of the reference signal received. Outputs of the sense amplifiers are provided through data latch/buffers 220 to the processor 214, enabling the processor 214 to determine from the sense amplifier outputs the threshold state of the cell being read.
In a known manner for program-verifying as discussed above, MLC designs require verify cycles after each program pulse for each Vt level in the MLC array. For storage of N logical in the MLC flash memory cell, Nxe2x88x921 verify cycles are necessary. Each verify cycle requires time for bit-line preparation and voltage level setup time. As the N number of the bits stored in the memory cell increases, the verify time increases proportionally. Accordingly, there is a need in the art for a circuit and method for reducing verify time in a MLC flash memory device and allow all Nxe2x88x921 levels to be verified concurrently.
One aspect of the present invention regards a semiconductor memory device comprising a plurality of flash memory cells operative for storing one or more logical bits of data and a staircase program-verify circuit for concurrently verifying programming of the one or more bits of data in each of the plurality of flash memory cells. Flash memory cells operative for storing multiple bits of logical data within a single memory cell are known in the art and commonly referred to as multilevel cell (MLC) flash memory. The plurality of MLC flash memory cells collectively is commonly referred to as a MLC flash memory array. MLC flash memory designs comprise at least one storage element that is programmable to any one of distinct multiple states. The multiple programmable states are commonly referred to as levels. Each programmable level represents a distinct combination of logical bits. Data is stored in a MLC flash memory design by programming the memory cell to a selected level representative of the combination of logical bits to be stored within the MLC flash memory cell. By way of example, a MLC flash memory cell designed for storing two logical bits of data can store the logical bit combination xe2x80x9c01xe2x80x9d by programming the MLC flash memory cell to a selected level representative of that logical bit combination.
The staircase program-verify circuit is operative to verify that the MLC flash memory cell has been programmed to the selected level representative of the logical bit combination to be stored by the MLC flash memory cell and inhibit further programming of the MLC flash memory cell. The staircase program-verify circuit is further operative to concurrently verify programming of each of the discrete multiple programmable levels in the plurality of MLC flash memory cells by applying a single stepped voltage pulse to the MLC flash memory cells to complete all program level evaluations. A distinct programmable level is verified prior to each step of the pulse. The initial value of the stepped voltage pulse is selected to be within a range substantially equivalent to that necessary to read data from the highest programmable level of the MLC flash memory cell and preferably within a range to provide a read margin to compensate for functional variations and reliability concerns. Each subsequent voltage level of the stepped voltage pulse is within a range substantially equivalent to a voltage necessary to read data from the next lowest programmable level preferably within a range to provide a read margin to compensate for functional variations and reliability concerns. The program-verify circuit evaluates the programming of each level, verifies that the MLC flash memory cell is programmed to a desired level and inhibits that verified MLC flash memory cell from further programming pulses. Accordingly, the staircase program-verify circuit concurrently verifies all programmed levels of the MLC flash memory array and thereby increases verify performance.
A second aspect of the present invention is a method of concurrently verifying programming of each of the multiple programmable levels in a MLC flash memory array. The method comprises verifying programming of the highest program level in the MLC flash memory array to inhibit further programming of MLC flash memory cells that are verified as programmed for the highest level, and verifying each next lowest significant program level to inhibit further programming of MLC flash memory cells that are verified as programmed for that level until each significant program level has been verified.
One example of the method for concurrently verifying the programming of MLC flash memory designs comprises the step of applying a single stepped voltage pulse to the MLC flash memory array. The stepped voltage pulse has an initial value within a range substantially equivalent to that necessary to read data from the highest programmable level of the MLC flash memory cell and preferably within a range to provide a read margin to compensate for functional variations and reliability concerns. Each subsequent voltage level of the stepped voltage pulse is within a range substantially equivalent to a voltage necessary to read data from the next lowest programmable level preferably within a range to provide a read margin to compensate for functional variations and reliability concerns. At each step of the voltage pulse, a distinct programming level is evaluated and the MLC flash memory cells programmed to that level are inhibited from further programming pulses. The evaluation process continues by stepping down the voltage pulse to the next lowest level and inhibiting further programming of MLC flash memory cells programmed to that level until each significant program level is verified. Accordingly, this method allows for preclusion of programming of memory cells that have been verified as programmed and increases the performance for program-verifying of a MLC flash memory design.
The foregoing discussion of the summary of the invention has been provided only by way of introduction. Nothing in this section should be taken as a limitation on the claims, which define the scope of the invention. Additional objects and advantages of the present invention will be set forth in the description that follows, and in part will be obvious from the description, or may be learned by practice of the present invention. The objects and advantages of the present invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the claims.